Evolution of the design of a second generation FireWire based data acquisition system

Our laboratory has previously reported on the basic design concepts of an updated FireWire based data acquisition system for depth-of-interaction detector systems designed at the University of Washington. The new version of our data acquisition system leverages the capabilities of modern field programmable gate arrays (FPGA) and puts almost all functions into the FPGA, including the FireWire elements, the embedded processor, and pulse timing and integration. The design is centered around an acquisition node board (ANB) that includes 64 serial ADC channels, one high speed parallel ADC, FireWire 1394b support, the FPGA, a serial command bus and signal lines to support a rough coincidence window implementation to reject singles events from being sent on the FireWire bus. Adapter boards convert detector signals into differential paired signals to connect to the ANB. In this paper we discuss many of the design details, including steps taken to minimize the number of layers in the printed circuit board and to avoid skewing of parallel signals and unwanted bandwidth limitations.