Design and optimization of low-voltage two-stage CMOS amplifiers with enhanced performance

Author

Tavares, R. ; Vaz, B. ; Goes, J. ; Paulino, N. ; Steiger-Garcao, A.

Volume

1

fYear

2003

fDate

25-28 May 2003

Abstract

This paper presents a novel method for designing and optimizing high-speed low-voltage two-stage amplifiers with enhanced performance. On the one hand, at circuit level, an additional degree-of-freedom is added to the topology that allows reaching, simultaneously, high DC gain and fast settling response without increasing the power dissipation. On the other hand, an efficient method for optimizing the settling-response of the amplifiers in the time-domain is presented. A design example with simulated results is finally shown to validate the proposed ideas.

Keywords

CMOS analogue integrated circuits; circuit optimisation; high-speed integrated circuits; integrated circuit design; low-power electronics; operational amplifiers; time-domain synthesis; DC gain; OTA; design optimization; high-speed low-voltage two-stage CMOS amplifier; power dissipation; settling time; time domain analysis; CMOS technology; Circuit topology; Design methodology; Design optimization; Electronic mail; Power dissipation; Power system reliability; Sampling methods; Time domain analysis; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1205534

Filename

1205534