DocumentCode
3533555
Title
A toolset for the analysis and optimization of motion estimation algorithms and processors
Author
Spiteri, Trevor ; Vafiadis, George ; Nunez-Yanez, Jose Luis
Author_Institution
Dept. of Electr. & Electron. Eng., Univ. of Bristol, Bristol, UK
fYear
2009
fDate
Aug. 31 2009-Sept. 2 2009
Firstpage
423
Lastpage
428
Abstract
This paper presents a reconfigurable processor designed to execute user-defined block-matching motion estimation algorithms, and a toolset for the design of such algorithms and for the configuration of the processor. The toolset enables the exploration of the processor´s design space in order to find an optimal configuration depending on the target application. The use of the toolset to test different configurations for different kinds of video sequences is illustrated. Experimental results show the benefits and cost of certain optimizations in the motion estimation process, and that fast block-matching search algorithms can outperform full search algorithms commonly used in hardware implementations. The usefulness of the toolset in exploring the configuration space is also shown.
Keywords
image matching; image sequences; logic design; microprocessor chips; motion estimation; search problems; fast block-matching search algorithm; motion estimation algorithm; processors design; reconfigurable processor; user-defined block-matching algorithm; video sequences; Algorithm design and analysis; Computer architecture; Design optimization; Hardware; Motion estimation; Process design; Rate-distortion; Space exploration; Systolic arrays; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on
Conference_Location
Prague
ISSN
1946-1488
Print_ISBN
978-1-4244-3892-1
Electronic_ISBN
1946-1488
Type
conf
DOI
10.1109/FPL.2009.5272247
Filename
5272247
Link To Document