Testable Design and BIST Techniques for Systolic Motion Estimators in the Transform Domain

Testable design techniques for systolic motion estimators based on M-testability conditions are proposed in this paper. The whole motion estimator can be viewed as a two-dimensional iterative logic array (ILA) of processing elements (PEs) and multiplying elements (MULs). The functions of each processing element and multiplying elements are modified to be bijective to meet the M-testable conditions. The number of test patterns is 2^w, where w denotes the wordlength of a PE. The proposed testable design techniques are also suitable for built-in self-test implementation. According to experimental results, our approaches can achieve 99.27% fault coverage. The area overhead is about 9%. To verify our approaches, an experimental chip is also implemented.