Design and evaluation of an energy-efficient dynamically reconfigurable architecture for wireless sensor nodes

We explore the design of a coarse-grained reconfigurable architecture for wireless sensor network nodes, which combines high energy efficiency with programmability and hence meets the requirements of small energy-constraint embedded systems. Its energy consumption, area, and performance are evaluated and compared to processor and ASIC architectures. Our case study particularly focuses on the question if the architecture concept of frequent dynamic reconfiguration of a small heterogeneous data path can lead to suitable system solutions for the target domain. To answer this, the effect of the reconfiguration overhead on total system efficiency is examined closely. As important result, our experiments show the low energy consumption achieved, the low reconfiguration overhead, and the specific region of the architecture in the design space between processors and ASICs. In particular, large energy-savings of factor 2 to 6 and speed-ups of factor 6 to 14 compared to processors are obtained on average. Our work shows the high suitability of frequent runtime reconfiguration of small coarse-grain data paths for the design of very efficient but yet programmable embedded systems platforms.