Title :
Algorithm acceleration on LEON-2 processor using a reconfigurable bit manipulation unit
Author :
Cardarilli, G.C. ; Nunzio, L. Di ; Fazzolari, R. ; Re, M.
Author_Institution :
Dept. of Electron. Eng., Univ. of Rome Tor Vergata, Rome, Italy
Abstract :
Advanced bit manipulation operations are not efficiently supported by standard microprocessors since they are optimized for fixed data size operations. In literature several hardware solutions are proposed to overcome this problem, and. In this work we present the experimental results of a new architecture based on LEON-2 and a simplified version of ADAPTO (Adder-based Dynamic Architecture for Processing Tailored Operators), acting as a co-processor. For our experiments we run a set of Bit Manipulation Algorithms on the LEON-2 processor in presence and absence of the ADAPTO unit. This permits to measure the speed-up factor obtained using the proposed reconfigurable co-processor.
Keywords :
coprocessors; reconfigurable architectures; ADAPTO; LEON-2 processor; microprocessors; reconfigurable bit manipulation unit; reconfigurable co-processor; Acceleration; Clocks; Computer architecture; Coprocessors; Data engineering; Field programmable gate arrays; Hardware; Microprocessors; Reconfigurable architectures; Table lookup;
Conference_Titel :
Intelligent Solutions in Embedded Systems (WISES), 2010 8th Workshop on
Conference_Location :
Heraklion, Crete
Print_ISBN :
978-1-4244-5715-1
Electronic_ISBN :
978-1-4244-5717-5
DOI :
10.1109/WISES.2010.5548433
