In field, energy-performance tunable FPGA architectures

Energy-performance tunable circuits enable the user to adjust the energy and performance of a chip after fabrication to suite the particular application, thus increase the overall power efficiency of the chip. Two tunable interconnect architectures are proposed. Pseudo-static interconnect achieves the same performance as static interconnect while consuming only 65% as much energy and provides 2X wider range for adjusting energy performance. Integration of pseudo-static interconnect in FPGA architecture does not require any system level changes. Pulse-mode interconnect provides marginal improvement at comparable power consumption but provides considerable performance boost when energy increases. Using pulses enables pulse-mode lookup tables with 2.5X higher speed at 2X higher power consumption and at the cost of significant system level changes.