DocumentCode :
3533972
Title :
Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays
Author :
Van Essen, Brian ; Wood, Aaron ; Carroll, Allan ; Friedman, Stephen ; Panda, Robin ; Ylvisaker, Benjamin ; Ebeling, Carl ; Hauck, Scott
Author_Institution :
Dept. of Comput. Sci. & Eng., Univ. of Washington, Seattle, WA, USA
fYear :
2009
fDate :
Aug. 31 2009-Sept. 2 2009
Firstpage :
268
Lastpage :
275
Abstract :
Spatially-tiled architectures, such as coarse-grained reconfigurable arrays (CGRAs), are powerful architectures for accelerating applications in the digital-signal processing, embedded, and scientific computing domains. In contrast to field-programmable gate arrays (FPGAs), another common accelerator, they typically time-multiplex their processing elements and are word rather than bit-oriented. These differences lead us to re-examine some of the traditional architecture choices made for FPGAs as we move to these coarser-granularity architectures. In this paper we study the efficiency of time-multiplexing global interconnect as architectures scale from single-bit to multi-bit datapaths. Using the Mosaic infrastructure, we analyzed the design trade-offs involved in static vs. time-multiplexed routing for global interconnect channels, as well as the benefit of including a dedicated bit-wide control interconnect to supplement the word-wide datapath of a CGRA. We show that a time-multiplexed interconnect is beneficial in these coarse-grained systems, reducing the area-energy product to 0.32times the area-energy product of a fully static interconnect. We also show that for our benchmarks, which include single-bit control logic, providing both word and bit-wide interconnect resources further reduces the area-energy product to 0.94times that of an exclusively word-wide interconnect.
Keywords :
field programmable gate arrays; multiprocessor interconnection networks; reconfigurable architectures; scheduling; FPGA; Mosaic infrastructure; coarse-grained reconfigurable arrays; coarser-granularity architectures; dedicated bit-wide control interconnect; digital-signal processing; field-programmable gate arrays; global interconnect channel; time-multiplexed interconnect; time-multiplexed routing; time-multiplexing global interconnect; Clocks; Computer architecture; Energy efficiency; Field programmable gate arrays; Integrated circuit interconnections; Logic arrays; Logic programming; Processor scheduling; Routing; Scientific computing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on
Conference_Location :
Prague
ISSN :
1946-1488
Print_ISBN :
978-1-4244-3892-1
Electronic_ISBN :
1946-1488
Type :
conf
DOI :
10.1109/FPL.2009.5272293
Filename :
5272293
Link To Document :
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