• DocumentCode
    3533992
  • Title

    A persistent rescheduled-page cache for low overhead object code compatibility in VLIW architectures

  • Author

    Conte, Thomas M. ; Sathaye, Sumedh W. ; Banerjia, Sanjeev

  • Author_Institution
    Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
  • fYear
    1996
  • fDate
    2-4 Dec 1996
  • Firstpage
    4
  • Lastpage
    13
  • Abstract
    Object-code compatibility between processor generations is an open issue for VLIW architectures. A potential solution is a technique termed dynamic rescheduling, which performs run-time software rescheduling at the first-time page faults. The time required for rescheduling the pages constitutes a large portion of the overhead of this method. A disk caching scheme that uses a persistent rescheduled-page cache (PRC) is presented. The scheme reduces the overhead associated with dynamic rescheduling by saving rescheduled pages on disk, across program executions. Operating system support is required for dynamic rescheduling and management of the PRC. The implementation details for the PRC are discussed. Results of simulations used to gauge the effectiveness of PRC indicate that: the PRC is effective in reducing the overhead of dynamic rescheduling; and due to different overhead requirements of programs, a split PRC organization performs better than a unified PRC. The unified PRC was studied for two different page replacement policies: LRU and overhead-based replacement. It was found that with LRU replacement, all the programs consistently perform better with increasing PRC sizes, but the high-overhead programs take a consistent performance hit compared to the low-overhead programs. With overhead-based replacement, the performance of high-overhead programs improves substantially, while the low-overhead programs perform only slightly worse than in the case of the LRU replacement
  • Keywords
    cache storage; operating systems (computers); paged storage; parallel architectures; program compilers; scheduling; software performance evaluation; software portability; LRU replacement; VLIW architectures; disk caching scheme; dynamic rescheduling; first-time page faults; high-overhead programs; low overhead object code compatibility; operating system support; overhead-based replacement; page replacement policies; persistent rescheduled-page cache; program executions; program performance; run-time software rescheduling; simulations; Computer architecture; Delay; Dynamic scheduling; Hardware; Operating systems; Partial response channels; Processor scheduling; Program processors; Runtime; VLIW;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microarchitecture, 1996. MICRO-29.Proceedings of the 29th Annual IEEE/ACM International Symposium on
  • Conference_Location
    Paris
  • Print_ISBN
    0-8186-7641-8
  • Type

    conf

  • DOI
    10.1109/MICRO.1996.566445
  • Filename
    566445