A novel SRAM-based FPGA architecture for efficient TMR fault tolerance support

This paper proposes a novel SRAM based FPGA architecture that is suitable for mapping designs when fault tolerance is desirable. TMR has been successfully applied in FPGAs to mitigate transient faults, which are likely to occur in harsh environments such as in space applications. In addition, fault tolerance techniques gain importance as feature sizes shrink and make circuits less reliable. However, TMR comes at high area penalty, which increases as the TMR grain becomes finer. We propose a slight modification to existing SRAM based FPGA architectures to support fine grain redundancy at an area cost even less than 3times (1.76times in average for our benchmark circuits). Our approach also provides accurate fault location and allows smaller and more infrequent reconfigurations saving both reconfiguration time and power.