Improving the memory footprint and runtime scalability of FPGA CAD algorithms

Advances in process technology have allowed for a dramatic increase in the capacity of FPGAs and this scaling is continuing at a steady pace. However, this scaling places increasing demands on the FPGA CAD tools. Already, for very large designs, compile-times of an entire work day are common, and memory requirements that exceed what would be found in a common desktop workstation are the norm. As FPGAs continue to grow, the problem will become worse. Unless the scalability of FPGA CAD tools is addressed, the long run times and large memory footprints will become a hindrance to future FPGA scaling, leading to increased costs and design times for companies who use these devices. The proposed research focuses on both the memory and runtime scalability of FPGA CAD tools. We have presented work on effective methods to improve the memory scalability. This work is summarized in Section 3. We are currently focusing on the runtime scalability portion of the project. Our current progress and proposed research on this part was summarized in Section 4.