Design evaluation of pipelined processors using finite state machine analysis with Markov chains

Performance evaluation of processor pipelines is required to scrutinize new and existing designs. General techniques of performance evaluation, simulation and analytical, have their strengths and weaknesses. Simulation is recommended for accurate results during final testing, while analytical is recommended for fast response time in early testing. This paper presents an analytical technique for determining processor pipeline performance that can reduce time and cost in the early design cycle when rapid response to “what if?” questions is most beneficial to the designer. The analytic model starts with a processor pipeline modeled as a finite state machine (FSM) that can be mapped on to a discrete-time Markov chain. The pipeline state model is described in detail. Large instruction traces are analyzed to extract the state transition probabilities for the Markov chain. Utilizing the properties of the Markov chain, the steady state probabilities can then be determined. The steady state probabilities are use to determine such measures as clocks per instruction, stage utilization, blocking and efficiency of the pipeline. Delays due to cache misses, true dependencies and branching can also be incorporated in the solution. An implementation of the Markov chain based dynamic instruction trace analyzer for MIPS R2000/R3000 is described and its results are presented