Design and implementation of 32nm FINFET based 4×4 SRAM cell array using 1-bit 6T SRAM

Author

Deepak, A. Lourts ; Dhulipalla, Likhitha

Author_Institution

VLSI Syst. Design, M.S. Ramaiah Sch. of Adv. Studies, Bangalore, India

fYear

2011

fDate

28-30 Nov. 2011

Firstpage

177

Lastpage

180

Abstract

A Static Random Access Memory (SRAM) is designed to plug two needs: i) The SRAM provides as cache memory, communicating between central processing unit and Dynamic Random Access Memory (DRAM), ii) The SRAM technology act as driving force for low power application since SRAM is portable compared to DRAM, and SRAM doesn´t require any refresh current. In this paper, we´ve illustrated the design and implementation of FINFET based 4×4 SRAM cell array by means of one bit 6T SRAM. It has been carried out by FINFET HSPICE modeling with read and write operation of SRAM memory.

Keywords

MOSFET; SRAM chips; cache storage; low-power electronics; 6T SRAM; DRAM; FinFET based 4×4 SRAM cell array; HSPICE modeling; cache memory; central processing unit; dynamic random access memory; low power application; read operation; size 32 nm; static random access memory; word length 1 bit; write operation; Arrays; FinFETs; Inverters; Logic gates; Random access memory; Silicon; 1-BIT 6T SRAM; 4×4 6 Transistor SRAM Cell; FINFET; SRAM;

fLanguage

English

Publisher

ieee

Conference_Titel

Nanoscience, Engineering and Technology (ICONSET), 2011 International Conference on

Conference_Location

Chennai

Print_ISBN

978-1-4673-0071-1

Type

conf

DOI

10.1109/ICONSET.2011.6167948

Filename

6167948