Design and estimation of drive current of scaled devices by selection of suitable metal gate with ZrO2 dielectric in nm regime

CMOS technology has witnessed aggressive scaling over the last couple of decades. This has resulted in better performance, higher integration density and increased onchip functionality. Besides this threshold voltage scaled down, oxides drastically thinned and MOS transistor channels have been meeting to the high performance criteria. However, all these have resulted in an increase in transistor leakage. This paper explores the design and estimation of drive current of scaled devices by selecting the suitable metal for gate with ZrO2 in nm range. Each metal have different work function, high work function sifts the threshold voltage and reduce the drive current. In this paper we have performed comparative analysis of four devices of different combinations NMOS/ ZrO2/Titanium, NMOS/ZrO2/Beryllium, NMOS/ ZrO2/Nickel, NMOS/ ZrO2/Selenium, with NMOS/SiO2, in 25 nm node and found that titanium metal gate is best combination to improve the device performance.