ePASS-a software-based POWER simulator

The latest RISC computer chips provide very high performance though complex pipelined implementations, using independent integer and floating point units, branch prediction mechanisms, multiple instruction dispatch per clock cycle and more. For a chosen hardware configuration to deliver optimized performance, various design aspects, resulting in many possible configurations, need to be thoroughly evaluated. Among these are such issues as synchronization between pipelines, cache organization and access policy, dynamic vs static branch prediction, detecting and handling dependency among instructions in different pipeline states. Addressing the above necessitates the use of simulators that provide the design environment in which to model and evaluate candidate configurations and then fine-tune the chosen implementation. The authors describe ePASS, an experimental software based simulator for the IBM RS/6000 and its POWER architecture. They discuss the three basic modules ePASS consists of, each representing a different view of the system: an Instruction Interpreter and Register Set Simulator, a Functional Simulator and a Memory Simulator. Finally they present a simple test case program to run on the simulator, involving branch prediction and execution as well as making use of the interlock mechanism to guarantee synchronization of the branch unit with the fixed point pipeline