Compensating for variability in FPGAs by re-mapping and re-placement

Author

Sedcole, Pete ; Stott, Edward ; Cheung, Peter Y K

Author_Institution

Dept. Electr. & Electron. Eng., Imperial Coll. London, London, UK

fYear

2009

fDate

Aug. 31 2009-Sept. 2 2009

Firstpage

613

Lastpage

616

Abstract

Two complementary techniques for reducing the effect of within-die variability on the critical path delay in FPGA circuits are reported. The first technique selects the best LUT mapping from a set of alternative mappings of a logic function for each LUT cluster in the FPGA. The second selects the best assignment of LUTs to physical locations within a cluster. The techniques can be used together, and are shown in Monte Carlo experiments to reduce both the mean and standard deviation of critical path delay.

Keywords

Monte Carlo methods; field programmable gate arrays; table lookup; FPGA circuit; LUT cluster; LUT mapping; Monte Carlo experiment; complementary technique; critical path delay; logic function; mean deviation; path reconfiguration; re-mapping technique; re-placement technique; standard deviation; variation compensation; within-die variability; Circuits; Delay effects; Educational institutions; Field programmable gate arrays; Logic functions; Monte Carlo methods; Nanostructured materials; Propagation delay; Table lookup; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on

Conference_Location

Prague

ISSN

1946-1488

Print_ISBN

978-1-4244-3892-1

Electronic_ISBN

1946-1488

Type

conf

DOI

10.1109/FPL.2009.5272380

Filename

5272380