Mapping basic prefix computations to fast carry-chain structures

Carry chains are a standard feature of modern FPGA architectures. They enable compact, regular and yet very fast implementations of the binary word addition even outpacing sophisticated parallel prefix networks for bit width far beyond 100. Although they are equally suited for other simple prefix computations, their employment in the implementation of such user functions is hindered by unportable low-level and vendor- or even device-specific means to implement the desired mapping. This paper names suitable example applications, identifies the class of prefix computations generically mappable to carry chains and presents a universal procedure to achieve this mapping by a transformation building upon the well-supported binary word addition. Synthesis results are presented to illustrate both the gain in speed and the significant reduction of area through the employment of this approach.