A novel SEU, MBU and SHE handling strategy for Xilinx Virtex-4 FPGAs

Author

Iturbe, X. ; Azkarate, M. ; Martínez, I. ; Perez, J. ; Astarloa, A.

Author_Institution

Embedded Syst.-on-Chip Group, IKERLAN-IK4 Res. Alliance, Arrasate-Mondragon, Spain

fYear

2009

fDate

Aug. 31 2009-Sept. 2 2009

Firstpage

569

Lastpage

573

Abstract

This paper presents a new single event upset (SEU), multiple bit upset (MBU) and single hardware error (SHE) mitigation strategy to be used in Virtex-4 FPGAs. This strategy aims to increase not only the effectiveness of traditional triple module redundancy (TMR), but also the overall system availability. Frame readback with ECC detection and frame scrubbing are combined in a dynamically reconfigurable TMR architecture, designed under both spatial and implementation diversification premises. Moreover, since the strategy works on the device´s bitstream domain, the basis for Virtex-4 FPGAs bitstream definition are also shown.

Keywords

fault tolerant computing; field programmable gate arrays; redundancy; ECC detection; Xilinx Virtex-4 FPGA; bitstream domain; dynamically reconfigurable TMR architecture; frame readback; frame scrubbing; multiple bit upset; single event upset; single hardware error; triple module redundancy; Automatic logic units; Circuit faults; Consumer electronics; Error correction codes; Field programmable gate arrays; Logic design; Logic devices; Random access memory; Reconfigurable logic; Single event upset;

fLanguage

English

Publisher

ieee

Conference_Titel

Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on

Conference_Location

Prague

ISSN

1946-1488

Print_ISBN

978-1-4244-3892-1

Electronic_ISBN

1946-1488

Type

conf

DOI

10.1109/FPL.2009.5272410

Filename

5272410