The educational processor Sweet-16

A 16-bit fully functional one cycle RISC processor was developed for the illustration and use in computer architecture classes. It is simple enough so that it can be designed by entry level students without any prerequisites as home assignment. In addition its architecture is optimized to support the computer architecture curriculum with concrete practical hands-on experiments. The processor is subsequently used for assembly language home work. The architecture has upgrade options for advanced studies, such as pipelining, interrupts, etc. This paper presents the architecture of this unique processor Sweet-16¹, its existing programming and design infrastructure and the teaching experience, based on by now more than 600 completed versions. Our experience over the years is that interested students very much appreciate the Sweet-16 exercise.