Multi Vt 7T Sram cell for high speed application at 45 Nm technology

The trend of decreasing device size and increasing chip densities involving several hundred millions of transistors per chip has resulted in tremendous increase in design complexity. Low power SRAMs are essential in today´s demand as they are preferred as on chip memories with read write stability. This paper presents a method based on multi-Vt to increase read, write stability and reduce the total leakage power dissipation of SRAMs while maintaining their performance. The proposed method is based on the observation that read and write delays of a memory cell in an SRAM block depend on the physical distance of the cell from the sense amplifier and it is also depend on Vt.