Read write stability with leakage minimization of 4t Sram cell for nano Cmos technology

The trend of decreasing device size and increasing chip densities involving several hundred millions of transistors per chip has resulted in tremendous increase in design complexity. The advancement of CMOS technology has driven chip design to achieve higher integration, faster performance, and lower power consumption. Low power SRAMs are essential in today´s demand as they are preferred as on chip memories with read write stability. The new cell size is 35.45% smaller than a conventional six-transistor cell using same design rules. Also proposed cell uses two word-lines and one pair bit-line, write operation perform from one side of cell, and Read operation perform from another side of cell, and swing voltage reduced on word-lines thus power during read/write operation reduced. Cadence Virtuoso simulation in standard 45nm CMOS technology confirms all results obtained from this paper.