Modeling of power converters for debugging digital controllers through FPGA emulation

Debugging a digital controller for power converters can be a lengthy process due to the long time required in mixed-signal simulations. This paper focuses on the design of a power converter model for debugging digital controllers in closed loop. The testing may be performed by means of simulation or emulation. This paper shows the results of simulating and emulating the power converter using different data representations. Experiments will show that through a good selection of data and emulation, testing can be speeded up over 28,000 times.