Specific power illustration of proposed 7T SRAM with 6T SRAM using 45 nm technology

Author

Akashe, Shyam ; Rastogi, Shishir ; Sharma, Sanjay

Author_Institution

Inst. of Technol. & Manage., Gwalior, India

fYear

2011

fDate

28-30 Nov. 2011

Firstpage

364

Lastpage

369

Abstract

This paper is based on the observation of a various CMOS seven transistor SRAM cell for very high density and low power applications. This cell retains its data with leakage current and positive feedback without refresh cycle. These various 7T SRAM cell uses one word-line and one bit-line and NMOS transistor to control. Simulation and analytical results show purposed cell has correct operation during read/write and also the delay of new cell is 70.15% smaller than a six-transistor SRAM cell. The various new 7T SRAM cell contains 72.10% less leakage current with respect to the 6T SRAM memory cell using cadence 45 nm technology and power consumption during read and write operation are approximate 20.34% less than the conventional 6T SRAM memory cell.

Keywords

CMOS memory circuits; MOSFET; SRAM chips; delays; feedback; leakage currents; low-power electronics; 6T SRAM memory cell; CMOS 7T SRAM memory cell; CMOS seven transistor SRAM memory cell; NMOS transistor; cell delay; leakage current; low power application; one bit-line; one word-line; positive feedback; power consumption; read-write operation; six-transistor SRAM memory cell; size 45 nm; CMOS integrated circuits; Degradation; Delay; MOS devices; Random access memory; Very large scale integration; Cell area; Cell delay; Cell leakage; Various 7T SRAM cell; power consumption;

fLanguage

English

Publisher

ieee

Conference_Titel

Nanoscience, Engineering and Technology (ICONSET), 2011 International Conference on

Conference_Location

Chennai

Print_ISBN

978-1-4673-0071-1

Type

conf

DOI

10.1109/ICONSET.2011.6167982

Filename

6167982