Low frequency noise consideration for MOSFET analog circuits

Progress in higher level integration in digital CMOS technology has led to the implementation of mixed mode analog/digital circuit functions on the same chip. In order to fully realize the potential of analog applications of MOS FETs processed with digital technology, the impact of digital fabrication technology on device analog performance has to be examined. One of the essential processing issues is the plasma etching induced gate oxide damage, which affects MOSFET threshold voltage and 1/f noise. The 1/f noise is known to affect broad band circuit design and its intensity poses a limit on input signal level, which will be further reduced in low power electronics. To alleviate the design constraints imposed by MOSFET noise, it is essential to examine the 1/f noise characteristics affected by the device design. In this paper, we report such an investigation, illustrating that the noise dependence on channel length, metal interconnect perimeter length, and gate bias needs to be taken into consideration for analog circuit design.