Using 3D integration technology to realize multi-context FPGAs

Author

Cevrero, Alesandro ; Athanasopoulos, P. ; Parandeh-Afshar, Hadi ; Skerlj, Maurizio ; Brisk, Philip ; Leblebici, Yusuf ; Ienne, Paolo

Author_Institution

Sch. of Eng., Ecole Polytech. Fed. de Lausanne (EPFL), Lausanne, Switzerland

fYear

2009

fDate

Aug. 31 2009-Sept. 2 2009

Firstpage

507

Lastpage

510

Abstract

This paper advocates the use of 3D integration technology to stack a DRAM on top of an FPGA. The DRAM will store future FPGA contexts. A configuration is read from the DRAM into a latch array on the DRAM layer while the FPGA executes; the new configuration is loaded from the latch array into the FPGA in 60 ns (5 cycles). The latency between reconfigurations, 8.42 mus, is dominated by the time to read data from the DRAM into the latch array. We estimate that the DRAM can cache 289 FPGA contexts.

Keywords

DRAM chips; cache storage; field programmable gate arrays; flip-flops; reconfigurable architectures; 3D integration technology; DRAM; cache storage; latch array; multicontext FPGA; time 60 ns; time 8.42 mus; Bonding; Context; Data mining; Decoding; Delay; Field programmable gate arrays; Integrated circuit interconnections; Latches; Random access memory; Tiles;

fLanguage

English

Publisher

ieee

Conference_Titel

Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on

Conference_Location

Prague

ISSN

1946-1488

Print_ISBN

978-1-4244-3892-1

Electronic_ISBN

1946-1488

Type

conf

DOI

10.1109/FPL.2009.5272454

Filename

5272454