DocumentCode
3535040
Title
InAs/GaAs graded superlattice channel transistors (GSTs)
Author
Ando, Y. ; Wakejima, A. ; Miura, I. ; Contrata, W. ; Miyamoto, H. ; Samoto, N.
Author_Institution
Kansai Electron. Res. Labs., NEC Corp., Otsu, Japan
fYear
1995
fDate
19-21 June 1995
Firstpage
40
Lastpage
41
Abstract
Pseudomorphic high electron mobility transistors (PHEMTs) offer superior power and noise performances compared to conventional HEMTs. However, as gate voltage increases, PHEMTs still suffer from parallel conduction of electrons in doped AlGaAs. This effect not only decreases transconductance (g/sub m/) at high gate bias but also degrades power gain and efficiency for large-signal operation. High indium content channel would allow an increase in conduction band offset, and hence, suppression of the parallel conduction, but due to the lattice mismatch, the reliability of the device might be affected, and therefore, the maximum allowable InAs mole fraction is limited. In this paper, we propose a graded superlattice channel transistor (GST), which reduces parallel conduction while suppressing an increase of strain in the channel.
Keywords
III-V semiconductors; gallium arsenide; high electron mobility transistors; indium compounds; semiconductor superlattices; InAs-GaAs; conduction band offset; efficiency; graded superlattice channel transistors; large-signal operation; lattice mismatch; parallel conduction; power gain; pseudomorphic high electron mobility transistors; reliability; strain; transconductance; Degradation; Electron mobility; Gallium arsenide; HEMTs; Indium; MODFETs; PHEMTs; Superlattices; Transconductance; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Device Research Conference, 1995. Digest. 1995 53rd Annual
Conference_Location
Charlottesville, VA, USA
Print_ISBN
0-7803-2788-8
Type
conf
DOI
10.1109/DRC.1995.496241
Filename
496241
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