High speed fixed point dividers for FPGAs

This paper presents a novel class of division algorithm that reduces the delay of calculus introducing more concurrency in computation. The algorithm is suitable for fixed-point operands and divides in a radix r = 2^k, producing k bits at each iteration. The proposed digit recurrence algorithm has two different architectures, a first one for general hardware implementation, and the second one optimized for configurable logic. Results show a speedup greater to three times respect to a classical non-restoring division implemented in Xilinx Devices. The dividers were also compared against Xilinx CoreGenerator circuits clearly outperforming latency and area.