DocumentCode
3535178
Title
A power-efficient architecture for high-speed D/A converters
Author
Farzan, Kamran ; Johns, David A.
Author_Institution
Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Volume
1
fYear
2003
fDate
25-28 May 2003
Abstract
A novel power-efficient architecture for high-speed D/A converters is proposed. A data look ahead technique is used to pre-switch the current sources so that the DAC current is reduced when generating small voltage levels. Interestingly, this technique also eliminates the need for a pre-driver block for each current-cell, which also saves power. Based on this architecture, a 6-bit DAC is designed in 0.18μm standard digital CMOS technology. The update rate for this DAC is 1GS/s and it consumes only 24mW at 1GS/s.
Keywords
CMOS integrated circuits; digital-analogue conversion; high-speed integrated circuits; 0.18 micron; 24 mW; 6 bit; CMOS technology; current source pre-switching; data look ahead technique; high-speed D/A converter; power-efficient architecture; Analog-digital conversion; CMOS technology; Costs; Energy consumption; Instruments; Power dissipation; Power generation; Power supplies; Tail; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN
0-7803-7761-3
Type
conf
DOI
10.1109/ISCAS.2003.1205709
Filename
1205709
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