DocumentCode
3535190
Title
Comparing fine-grained performance on the Ambric MPPA against an FPGA
Author
Hutchings, Brad ; Nelson, Brent ; West, Stephen ; Curtis, Reed
Author_Institution
Dept. of Electr. & Comput. Eng., Brigham Young Univ., Provo, UT, USA
fYear
2009
fDate
Aug. 31 2009-Sept. 2 2009
Firstpage
174
Lastpage
179
Abstract
A simple image-processing application is implemented on the Ambric MPPA and an FPGA, using a similar implementation for both devices. FPGAs perform extremely well on this kind of application and provide a good benchmark for comparison. The Ambric implementation starts out with a naive implementation and proceeds through several design optimizations until it reaches a maximum frame rate of 164 FPS (512 times 512 images) which turns out to be approximately 7times slower than the FPGA. The final Ambric implementation uses only 18 of 336 available processors, achieves more than sufficient performance for realtime embedded applications, and has excess processors to use for implementing additional algorithms. After introducing the image processing application and its implementation on both devices, the paper compares and contrasts the intrinsic, general characteristics of Ambric MPPA and FPGA devices.
Keywords
embedded systems; field programmable gate arrays; image processing; logic design; Ambric MPPA; FPGA; design optimization; fine-grained performance; image-processing application; massively parallel processor array; realtime embedded application; Application software; Application specific integrated circuits; Bandwidth; Design optimization; Digital signal processing; Field programmable gate arrays; High performance computing; Integrated circuit interconnections; Random access memory; Read-write memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on
Conference_Location
Prague
ISSN
1946-1488
Print_ISBN
978-1-4244-3892-1
Electronic_ISBN
1946-1488
Type
conf
DOI
10.1109/FPL.2009.5272505
Filename
5272505
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