An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs

Efficient cycle-based reconfiguration of datapaths can be realized on current FPGAs by designing merged datapaths, which can execute different tasks depending on the datapath control. In our previous work, we provided a synthesis tool for the automated generation of such datapaths. The objective in this paper is a reduction of the resource requirements for implementing the reconfiguration control on the FPGA. First, we extend our existing tool flow with a novel mechanism for efficient partial multi-context reconfiguration and provide tool support to generate according circuitry, control, and configuration data. Second, we propose an extension of current FPGA architectures to efficiently support cycle-based runtime control. We employ a special content-addressable multi-context memory resource for controlling the datapath functionality, which on average requires only 15% memory for storing the control data compared to a BlockRAM based approach, and only 53% compared to regular multi-context switching.