The evolution of architecture exploration of programmable devices

As integrated circuit fabrication processes continue to provide exponential increases in density of transistors with each generation, the question of what to do with those transistors becomes ever more interesting. The most fundamental part of that question is the global organization of the structures created from the transistors, most commonly referred to as the *architecture* of the device. Most IC architecture exploration that is done is quite empirical, with example uses driving through tools to experimentally test new ideas for structures and organizations. This method is used in both programmable logic hardware such as FPGAs, and in programmable instruction set processors. As the processor world now seeks to gain performance through parallelism, its architecture questions have begun to look more similar to those in the FPGA domain. In this talk the author discuss the evolution of the architecture exploration processes that we have worked on at the University of Toronto, and of the new levels that we are currently trying to build. The current effort focusses on HDL-level circuits as "example uses" and this turns out to be rather intricate in the face of the kinds of architecture questions that could be posed. In the future, it may well be that some form of software is the input "example use," thus bringing the processor and FPGA world closer together. For this to work, there needs to be an effective CAD/compiler flow from software to the HDL level. The author give perspective on the state of this art, and discuss what kind of commonality might evolve in architecture exploration tools for FPGAs and processors.