Implementation of Radix2 ACS in Adaptive Viterbi decoder

Author

Bobby, N.D. ; Srivatsa, S.K. ; Lalkishore

Author_Institution

Dept. of Electron. & Commun. Eng., T.J. Inst. of Technol., Chennai, India

fYear

2011

fDate

28-30 Nov. 2011

Firstpage

604

Lastpage

606

Abstract

Adaptive viterbi decoder is used for decoding codes of long constraint length, Where as viterbi decoder is used for decoding short constraint lengths. In order to minimize power consumption and BER, we have implemented Radix 2 ACS in viterbi decoder and Adaptive Viterbi decoder. The area consumption was less in viterbi compared to Adaptive Viterbi decoder. But the power utilization reduced drastically to 20% where as in Viterbi decoder the power consumed was 80%. In our previous work we have implemented Adaptive fast ACS, but the experimental result proves power consumption is less in radix 2 ACS in viterbi decoder and much less in Adaptive viterbi decoder.

Keywords

Viterbi decoding; adaptive codes; digital arithmetic; error statistics; BER; adaptive Viterbi decoder; adaptive fast ACS; power consumption minimization; power utilization reduction; radix2 ACS implementation; radix2 add-compare-select implementation; short constraint length decoding; Decoding; Table lookup; Viterbi algorithm; ACS Radix 2 ACS; AVD; FPGA; VLSI; Viterbi Decoding;

fLanguage

English

Publisher

ieee

Conference_Titel

Nanoscience, Engineering and Technology (ICONSET), 2011 International Conference on

Conference_Location

Chennai

Print_ISBN

978-1-4673-0071-1

Type

conf

DOI

10.1109/ICONSET.2011.6168043

Filename

6168043