A spur-free fractional-N ΣΔ PLL for GSM applications: linear model and simulations

A new PLL topology and a new simplified linear model are presented. The new ΣΔ fractional-N synthesizer presents no reference spurs and lowers the overall phase noise, thanks to the presence of a Sample/Hold block. With a new simulation methodology it is possible to perform very accurate simulations, whose results match closely those obtained with the linear PLL model developed.