Engineering single NMOS and PMOS output buffers for maximum failure voltage in advanced CMOS technologies

Author

Khazhinsky, Michael G. ; Miller, James W. ; Stockinger, Michael ; Weldon, James C.

Author_Institution

Freescale Semicond. Inc., Austin, TX, USA

fYear

2004

fDate

19-23 Sept. 2004

Firstpage

1

Lastpage

10

Abstract

In this paper we propose new circuit design options for increasing the ldquoeffectiverdquo failure voltage (Vt2) of both NMOS and PMOS output buffer transistors, thereby helping to protect these fragile devices. Using experimental data, device and circuit simulations we demonstrate how placing a series resistor and either a bias circuit for the buffer gates or secondary ESD diodes may significantly increase Vt2.

Keywords

CMOS integrated circuits; MOSFET; buffer circuits; electrostatic discharge; failure analysis; semiconductor device reliability; CMOS technology; PMOS output buffer transistor; buffer gate; circuit design option; maximum failure voltage; secondary ESD diode; series resistor; single NMOS output buffer transistor; CMOS technology; Circuit simulation; Circuit synthesis; Diodes; Electrostatic discharge; MOS devices; Protection; Resistors; Transistors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Overstress/Electrostatic Discharge Symposium, 2004. EOS/ESD '04.

Conference_Location

Grapevine, TX

Print_ISBN

978-1-5853-7063-4

Electronic_ISBN

978-1-5853-7063-4

Type

conf

DOI

10.1109/EOSESD.2004.5272600

Filename

5272600