Distributed gate ESD network architecture for inter-power domain signals

This paper examines the issue of transmitting signals between circuits of different power domains within an IC and the ESD sensitivity of the receiving logic´s oxide in advanced processes. It is also shown that the ESD stress voltage appearing across a receiving gate´s oxide can be distributed among several inverters. Also, design of interface attenuation networks that allow large voltage drops between domains for both CDM and HBM tests will be examined.