• DocumentCode
    3535908
  • Title

    ESD design automation for a 90nm ASIC design system

  • Author

    Brennan, Ciaran J. ; Kozhaya, Joseph ; Proctor, Robert ; Sloan, Jeffrey ; Chang, Shunhua ; Sundquist, James ; Lowe, Terry

  • Author_Institution
    IBM Microelectron., Essex Junction, VT, USA
  • fYear
    2004
  • fDate
    19-23 Sept. 2004
  • Firstpage
    1
  • Lastpage
    8
  • Abstract
    Design tools for ESD are described that ensure robust protection at both the cell and chip level in a high-volume, highly automated ASIC design system. There are three primary components: Design Rule Checking (DRC) for ESD; transient CDM simulations on extracted netlists; and analysis of chip-level power supply net resistances.
  • Keywords
    application specific integrated circuits; electrostatic discharge; integrated circuit design; ESD design automation; application specific integrated circuits; chip level protection; chip-level power supply net resistance; design rule checking; electrostatic discharge; size 90 nm; Analytical models; Application specific integrated circuits; Circuit simulation; Design automation; Electrostatic discharge; Immune system; Power supplies; Power system protection; Transient analysis; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrical Overstress/Electrostatic Discharge Symposium, 2004. EOS/ESD '04.
  • Conference_Location
    Grapevine, TX
  • Print_ISBN
    978-1-5853-7063-4
  • Electronic_ISBN
    978-1-5853-7063-4
  • Type

    conf

  • DOI
    10.1109/EOSESD.2004.5272614
  • Filename
    5272614
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3535908