GDFT types mapping algorithms and structured regular FPGA implementation

In this paper, regular and non-multiplicative mapping algorithms between different types of Generalized Discrete Fourier Transform (GDFT) are proposed. The proposed mapping algorithms are used to build regular and real twiddle factors FFT algorithms. It presents a mote regular FIT than the recently presented GDFT type-1, which in addition requires log (N/2) stages of permutation. Hardware realization of 16-point FFT, based on the proposed mapping algorithms, with real twiddle factors butterfly rather than complex twiddle factors in traditional FFT algorithms, is implemented in Xilinx XC4000 and Vertix series Field Programmable Gate Array (FPGA). Cost comparisons with alternative approaches are presented. Our proposed algorithms achieve a significant improvement in the FPGA-based designs.