GDFT types mapping algorithms and structured regular FPGA implementation

Author

Saleh, H.I. ; Ashour, M.A. ; Salama, A.E.

Author_Institution

AEA, NCRRT, Cairo, Egypt

Volume

4

fYear

2003

fDate

25-28 May 2003

Abstract

In this paper, regular and non-multiplicative mapping algorithms between different types of Generalized Discrete Fourier Transform (GDFT) are proposed. The proposed mapping algorithms are used to build regular and real twiddle factors FFT algorithms. It presents a mote regular FIT than the recently presented GDFT type-1, which in addition requires log (N/2) stages of permutation. Hardware realization of 16-point FFT, based on the proposed mapping algorithms, with real twiddle factors butterfly rather than complex twiddle factors in traditional FFT algorithms, is implemented in Xilinx XC4000 and Vertix series Field Programmable Gate Array (FPGA). Cost comparisons with alternative approaches are presented. Our proposed algorithms achieve a significant improvement in the FPGA-based designs.

Keywords

digital arithmetic; discrete Fourier transforms; field programmable gate arrays; GDFT types mapping algorithms; Generalized Discrete Fourier Transform; Vertix series; Xilinx XC4000; hardware realization; nonmultiplicative mapping algorithms; structured regular FPGA implementation; twiddle factors FFT algorithms; Algorithm design and analysis; Arithmetic; Cities and towns; Costs; Discrete Fourier transforms; Discrete transforms; Field programmable gate arrays; Flow graphs; Hardware; Sparse matrices;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1205790

Filename

1205790