ESD protection for a 5.5 GHz LNA in 90 nm RF CMOS — Implementation concepts, constraints and solutions

Author

Thijs, S. ; Natarajan, M.I. ; Linten, D. ; Vassilev, V. ; Daenen, T. ; Scholten, Andries ; Degraeve, R. ; Wambacq, P. ; Groeseneken, G.

Author_Institution

IMEC, Leuven, Belgium

fYear

2004

fDate

19-23 Sept. 2004

Firstpage

1

Lastpage

10

Abstract

Design and implementation of ESD protection for a 5.5 GHz Low Noise Amplifier (LNA) fabricated in a 90 nm RF CMOS technology is presented. An on-chip inductor, added as ldquoplug-and-playrdquo, is used as ESD protection for the RF pins. The consequences of design and process, as well as the limited freedom on the ESD protection implementation for all pins to be protected are presented in detail and additional improvements are suggested.

Keywords

CMOS integrated circuits; electrostatic discharge; inductors; low noise amplifiers; microwave amplifiers; microwave integrated circuits; ESD protection design; LNA fabrication; RF CMOS technology; RF pin; electrostatic discharge implementation; frequency 5.5 GHz; low noise amplifier; on-chip inductor; size 90 nm; CMOS technology; Circuit simulation; Electrostatic discharge; Inductors; Low-noise amplifiers; MOSFETs; Pins; Protection; Radio frequency; Radiofrequency amplifiers;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Overstress/Electrostatic Discharge Symposium, 2004. EOS/ESD '04.

Conference_Location

Grapevine, TX

Print_ISBN

978-1-5853-7063-4

Electronic_ISBN

978-1-5853-7063-4

Type

conf

DOI

10.1109/EOSESD.2004.5272635

Filename

5272635