• DocumentCode
    3536135
  • Title

    A new CMOS analog multiplier with improved input linearity

  • Author

    Jia, Xiang-Luan ; Huang, Wei ; Qin, Shi-Cai

  • Author_Institution
    Dept. of Electron Sci., Nankai Univ., Tianjin, China
  • fYear
    1995
  • fDate
    6-10 Nov 1995
  • Firstpage
    135
  • Lastpage
    136
  • Abstract
    A new CMOS four-quadrant analog multiplier is presented. By means of an unique nonlinear compensation technique, the linear input range of the multiplier is extended significantly. The simulation results show that, when Vy=±3V, the nonlinear error is less than 0.94% over the ±3V input range of Vx and when Vx =±3V, the nonlinear error is less than 0.25% over the ±3V input range of Vy, with a power supply of ±5V
  • Keywords
    CMOS analogue integrated circuits; analogue multipliers; error compensation; -3 to 3 V; -5 V; 5 V; CMOS analog multiplier; four-quadrant multiplier; input linearity improvement; linear input range; nonlinear compensation technique; nonlinear error; CMOS analog integrated circuits; CMOS process; Circuit simulation; Diodes; Linearity; MOSFETs; Mirrors; Power supplies; Signal processing; Tail;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microelectronics and VLSI, 1995. TENCON '95., IEEE Region 10 International Conference on
  • Print_ISBN
    0-7803-2624-5
  • Type

    conf

  • DOI
    10.1109/TENCON.1995.496355
  • Filename
    496355
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3536135