DocumentCode
3536169
Title
A 70 MS/s 8-bit differential switched-current CMOS A/D converter using parallel interleaved pipelines
Author
Bracey, M. ; Redman-White, W. ; Hughes, J.B. ; Richardson, J.
Author_Institution
Dept. of Electron. & Comput. Sci., Southampton Univ., UK
fYear
1995
fDate
6-10 Nov 1995
Firstpage
143
Lastpage
146
Abstract
A 70 MS/s CMOS A/D converter is presented. Four double-sampling differential switched-current pipelines are used in a time interleaved structure to achieve a high sampling rate. Particular issues addressed are the matching of signal copies whilst maintaining full analogue bandwidth, and minimising signal corruption during propagation. The experimental converter is fabricated in a standard 0.8 μm 5 V digital CMOS process without special options
Keywords
CMOS integrated circuits; analogue-digital conversion; pipeline processing; switched current circuits; 0.8 micron; 5 V; 8 bit; differential switched-current A/D converter; digital CMOS process; double-sampling pipelines; full analogue bandwidth; parallel interleaved pipelines; sampling rate; signal copies; signal corruption; time interleaved structure; Bandwidth; Circuits; Filters; Frequency conversion; Pipelines; Sampling methods; Signal resolution; Signal sampling; Switching converters; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronics and VLSI, 1995. TENCON '95., IEEE Region 10 International Conference on
Print_ISBN
0-7803-2624-5
Type
conf
DOI
10.1109/TENCON.1995.496358
Filename
496358
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