Hierarchical timing estimation using a module timing overlapping technique

Author

Kanthamanon, Prasert ; Hellestrand, Graham R. ; Chan, Ricky L K

Author_Institution

Sch. of Comput. Sci. & Eng., New South Wales Univ., Sydney, NSW, Australia

fYear

1995

fDate

6-10 Nov 1995

Firstpage

147

Lastpage

150

Abstract

This paper presents a novel timing estimation method for high level synthesis systems. The approach employs a hierarchical timing computation, and also supports timing information reusability across hierarchical levels. Therefore, it is suitable for use as part of a high level design methodology. The experimental results show that the timing estimation method is accurate when compared to gate level timing estimation

Keywords

high level synthesis; timing; hierarchical timing estimation; high level design methodology; high level synthesis systems; module timing overlapping technique; timing information reusability; Australia; Circuits; Computer science; Delay effects; Delay estimation; Hardware; High level synthesis; Laboratories; Timing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics and VLSI, 1995. TENCON '95., IEEE Region 10 International Conference on

Print_ISBN

0-7803-2624-5

Type

conf

DOI

10.1109/TENCON.1995.496359

Filename

496359

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3536178