FPGA-based Switched Reluctance Motor Drive and DC-DC converter models for high-bandwidth HIL real-time simulator

In this paper, we describe an FPGA implementation of a Switched Reluctance Motor Drive (SRM) and an H-bridge Buck-Boost converter targeted for Hardware-In-the Loop (HIL) testing of modern SRM controllers. These FPGA models allow the HIL simulation of SRM drive and boost converter with switching frequencies in the 50-100 kHz range because of the very high sampling rate of the FPGA. The models are also integrated into the RT-LAB realtime environment and directly linked with the simulator I/Os, providing ultra-low HIL gate-in-to-current-out latency, suitable for testing modern motor controllers.