High-performance microprocessor packaging in the year 2000: technical and economic barriers and alternatives

Author

Siu, Bill

Author_Institution

Assembly Technol. Dev., Intel Corp., Chandler, AZ, USA

fYear

1995

fDate

6-10 Nov 1995

Firstpage

234

Lastpage

237

Abstract

By the year 2000, computers capable of >1000 MIPs and operating at >500 MHz are on the horizon. As the microprocessor becomes more powerful, major technical and economic challenges in packaging technologies are evident. In this paper, we trace the emergence of the microprocessor by examining the technical and economical drivers. It is seen that specialized material processes and designs are required to package a high-performance microprocessor. Low-cost materials with low dielectric constant and high electrical and thermal conductivity metallization are required to meet these objectives. As microprocessor architectures migrate towards closely-coupled CPU/cache requiring more than one VLSI, the multichip module is emerging/re-emerging as a requirement

Keywords

VLSI; economics; integrated circuit manufacture; integrated circuit metallisation; integrated circuit packaging; microprocessor chips; multichip modules; technological forecasting; VLSI scaling; closely-coupled CPU/cache; economic barriers; high electrical conductivity metallization; high thermal conductivity metallization; high-performance microprocessor; low dielectric constant; low-cost materials; material processes; microprocessor architectures; microprocessor packaging; multichip module; packaging technologies; technical barriers; year 2000; Conducting materials; Dielectric materials; High-K gate dielectrics; Inorganic materials; Microprocessors; Packaging; Power generation economics; Power system economics; Process design; Thermal conductivity;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics and VLSI, 1995. TENCON '95., IEEE Region 10 International Conference on

Print_ISBN

0-7803-2624-5

Type

conf

DOI

10.1109/TENCON.1995.496381

Filename

496381