Hot electron induced channel length shortening model and its impact on HEIP in PMOS

Author

Park, J.T. ; Kim, Y.T. ; Kim, D.K. ; Hong, S.T. ; Yu, C.G.

Author_Institution

Dept. of Electron. Eng., Inchon Univ., South Korea

fYear

1995

fDate

6-10 Nov 1995

Firstpage

238

Lastpage

241

Abstract

A new analytical model based on a pseudo two dimensional model is presented for the hot electron induced channel length shortening (ΔL_H) of PMOSFET. It has been founded that ΔL_H is a logarithmic function of both the stress time and the degradation of punchthrough voltage, and is also a linear function of the degradation of the drain current. ΔL_H can be predicted from the measurement of the gate current (ΔL_H∝I_gⁿ) and can thus be used for the current calculation of a degraded PMOSFET

Keywords

MOSFET; electron traps; hot carriers; semiconductor device models; HEIP; PMOSFET; analytical model; bidirectional stress; current calculation; drain current degradation; gate current characteristics; hot electron induced channel length shortening model; hot electron induced punchthrough; pseudo two dimensional model; punchthrough voltage degradation; stress time; trapped electron charges; Analytical models; Current measurement; Degradation; Electron traps; Equations; Hot carriers; MOSFET circuits; Parameter extraction; Stress measurement; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics and VLSI, 1995. TENCON '95., IEEE Region 10 International Conference on

Print_ISBN

0-7803-2624-5

Type

conf

DOI

10.1109/TENCON.1995.496382

Filename

496382