Dependence of deep submicron CMOSFET characteristics on shallow source/drain junction depth

With the MOSES (Mask Oxide Sidewall Etch Scheme) process which uses a conventional i-line stepper and isotropic wet etching, CMOSFETs with fine gate patterns of 0.1 μm or less are fabricated and characterized successfully. To improve the short channel effect of 0.1 μm CMOS devices, the screening oxide is deposited before the low energy ion implantation for source/drain extensions and a two step sidewall scheme is adopted. Through the characterization of 0.1 μm CMOS devices, it is found that the screening oxide deposition scheme has a larger capability of suppressing the short channel effects than the two step sidewall scheme. In the case of 200 Å-thick screening oxide deposition, both NMOS and PMOS devices maintain good subthreshold characteristics down to 0.1 μm effective channel lengths, and show affordable drain saturation current reduction and low impact ionization rates