Hardware implementation of evolutionary digital filters

Author

Abe, Masahide ; Kawamata, Masayuki

Author_Institution

Dept. of Electron. Eng., Tohoku Univ., Sendai, Japan

Volume

4

fYear

2003

fDate

25-28 May 2003

Abstract

This paper designs and implements a hardware-based evolutionary digital filter (EDF). The EDF is an adaptive digital filter which is controlled by adaptive algorithm based on evolutionary computation. The hardware-based EDF consists of two submodules, that is, a filtering and fitness calculation (FFC) module and a reproduction and selection (RS) module. The FFC module has high computational ability to calculate the output and the fitness value since its submodules run in parallel. A synthesis result of the designed chip shows the clock frequency is 20.0 MHz and the maximum sampling rate of the EDF is 3.7 kHz. Moreover, the hardware-based EDF with 21 submodules of the FFC is 2.2 times faster than the software-based EDF.

Keywords

adaptive filters; digital filters; evolutionary computation; integrated circuit design; parallel processing; signal sampling; 20 MHz; 3.7 kHz; EDF; FFC module; RS module; adaptive digital filter; chip synthesis; clock frequency; computational ability; evolutionary computation based adaptive algorithm; evolutionary digital filters; filtering and fitness calculation module; hardware implementation; hardware-based EDF submodules; hardware-based evolutionary digital filter; parallel running submodules; reproduction and selection module; software-based EDF; Adaptive algorithm; Adaptive control; Clocks; Concurrent computing; Digital filters; Evolutionary computation; Filtering; Frequency synthesizers; Hardware; Programmable control;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1205857

Filename

1205857