Title :
A full digital self-timed clock generation scheme
Author :
Nahm, Seunghyeon ; Sung, Wonyong
Author_Institution :
Dept. of Control & Instrum. Eng., Seoul Nat. Univ., South Korea
Abstract :
A full digital self-timed clock generation scheme is developed, where multiple internal clocks are self-generated for each external request. The internal clock period is designed to be the critical path delay of the internal system at all operating environments. This scheme can be applied to time-multiplexed implementations, self-timed operation, and low-power applications
Keywords :
clocks; delays; digital integrated circuits; synchronisation; timing circuits; critical path delay; digital self-timed clock generation; low-power applications; multiple internal clocks; self-timed operation; time-multiplexed implementations; Arithmetic; Clocks; Delay; Frequency; Phase locked loops; Pulse circuits; Pulse generation; Signal generators; Signal processing; Timing;
Conference_Titel :
Microelectronics and VLSI, 1995. TENCON '95., IEEE Region 10 International Conference on
Print_ISBN :
0-7803-2624-5
DOI :
10.1109/TENCON.1995.496404
