Optimization of Low Power 7T SRAM Cell in 45nm Technology

In this paper a low power SRAM cell is proposed. In the proposed SRAM topology, additional circuitry has been added to a standard 6T-SRAM cell to improve the performance. A seven transistor (7T) cell at a 45nm feature size in CMOS is proposed to accomplish improvements in stability, power dissipation and performance compared with previous designs for low-power memory operation. By optimizing size and employing the proposed write circuitry scheme, a saving of 45% in power consumption is achieved in memory array operation compared with a conventional 6T SRAM based design. The impact of process variations is investigated in detail, and the CADENCE simulation shows that the 7T SRAM cell has an excellent tolerance to process variations.