Leakage Reduction in 7T Using SVL Scheme

High leakage currents in deep sub micron regimes are becoming a major contributor to total power dissipation of CMOS circuits as the threshold voltage, channel length and gate oxide thickness are scaled. Consequently, identification and modelling of different leakage components is very important for estimation and reduction of leakage power, especially for low power applications. In this work the impact of gate leakage on SRAM is described and two approaches for reducing gate leakage currents are examined in detail. In one approach, the supply voltage is reduced while in the other the potential of the ground node is raised. In both the approaches the effective voltage across SRAM cell is reduced in inactive mode using a dynamic self-controllable switch. CADENCE Simulations are performed with 180nm CMOS technology process file and the leakage currents of all the cells are measured and compared. Simulation results revealed that there is a significant reduction in leakage current for this proposed cell with the SVL circuit reducing the supply voltage.