Title :
Impact of Design Parameter on SRAM Bit Cell
Author :
Shrivas, Jayram ; Akashe, Shyam
Author_Institution :
M-Tech VLSI Design, Inst. of Technol. & Manage., Gwalior, India
Abstract :
SRAM Bit-Cell Sleep technique is widely used in processors to reduce SRAM leakage power. However, significance of leakage power savings from SRAM bit-cell sleep technique is dependent on process technology and various design parameters. This paper evaluates the effects of design parameters like ITD, DVS and VDCMIN_RET on performance of 7T SRAM bit-cell sleep technique. Impact of Process Technology on SRAM bit-cell sleep technique performance, due to transition from silicon dioxide (SIO2) to Hafnium based High-K gate dielectric material is also discussed in this paper. Hafnium is a chemical element and found in zirconium minerals, its atomic number is 72. Silicon measurement results of a 3MegaByte SRAM array designed in 45 nm High-K CMOS process is used to demonstrate reducing effectiveness of SRAM bit-cell sleep technique.
Keywords :
CMOS memory circuits; SRAM chips; arrays; electrical faults; hafnium; high-k dielectric thin films; silicon compounds; system-on-chip; 3MegaByte SRAM array design; 7T SRAM bit-cell sleep technique; Hf; SRAM leakage power; SiO2; chemical element; design parameters; hafnium-based high-K gate dielectric material; high-K CMOS process; process technology impact; silicon measurement; size 45 nm; zirconium minerals; Arrays; Floors; Leakage current; Logic gates; Random access memory; Switching circuits; Transistors; 7T SRAM bit cell; CMOS; SOC; SRAM;
Conference_Titel :
Advanced Computing & Communication Technologies (ACCT), 2012 Second International Conference on
Conference_Location :
Rohtak, Haryana
Print_ISBN :
978-1-4673-0471-9
DOI :
10.1109/ACCT.2012.63